We tackle the most complex problems in quantitative finance, by bringing scientific clarity to financial complexity.
From our London HQ, we unite world-class researchers and engineers in an environment that values deep exploration and methodical execution - because the best ideas take time to evolve. Together we’re building a world-class platform to amplify our teams’ most powerful ideas.
As part of our engineering team, you’ll shape the platforms and tools that drive high-impact research - designing systems that scale, accelerate discovery and support innovation across the firm.
The role
The Low Latency Engineering Group is responsible for a low-latency system that forms a critical part of our clients’ global investment platform. The group includes teams responsible for market-data, order-entry and order-execution functions.
This team has deployed a bespoke, cutting-edge FPGA-based platform that enables our clients to exploit low-latency opportunities in the most competitive markets in the world. The team is now expanding to accelerate the deployment of this platform more widely.
The LLE FPGA team is a small team of software and hardware engineers. It’s responsible for its own QA, tooling and continuous delivery pipelines. We value flexibility and willingness to collaborate on the problems we work on alongside our clients.
Key responsibilities of the role include:
Developing RTL HDL in SystemVerilog
Writing automated test benches
Writing scripts in Python
Developing software in C/C++
Building Continuous Delivery pipelines for all components
Who are we looking for?
You will be an enthusiastic and capable Engineer who is able to solve real-world problems in HDL and software. You should be flexible and proactive, with the ability to make complex systems work and to debug them when they don’t. You should enjoy working as part of a collaborative engineering team.
The ideal candidate will have the following skills and experience:
Practical experience of hardware/software co-design for FPGA-based systems
HDL development skills in SystemVerilog
Experience with Xilinx FPGA Build Process
System analysis and debugging skills
Ability to communicate well with technical and non-technical people
Experience working in a collaborative engineering team, preferably using a git-based development workflow
The following skills and experiences are beneficial, but not essential:
C or C++ knowledge
Python knowledge
Why should you apply?
Highly competitive compensation plus annual discretionary bonus
Lunch provided (via Just Eat for Business) and dedicated barista bar
35 days’ annual leave
9% company pension contributions
Informal dress code and excellent work/life balance
Comprehensive healthcare and life assurance
Cycle-to-work scheme
Monthly company events
